/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
 */

#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_GLYMUR_H
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_GLYMUR_H

/* CAM_CC clocks */
#define CAM_CC_BPS_AHB_CLK					0
#define CAM_CC_BPS_CLK						1
#define CAM_CC_BPS_CLK_SRC					2
#define CAM_CC_BPS_FAST_AHB_CLK					3
#define CAM_CC_CAMNOC_AXI_NRT_CLK				4
#define CAM_CC_CAMNOC_AXI_RT_CLK				5
#define CAM_CC_CAMNOC_AXI_RT_CLK_SRC				6
#define CAM_CC_CAMNOC_DCD_XO_CLK				7
#define CAM_CC_CAMNOC_XO_CLK					8
#define CAM_CC_CCI_0_CLK					9
#define CAM_CC_CCI_0_CLK_SRC					10
#define CAM_CC_CCI_1_CLK					11
#define CAM_CC_CCI_1_CLK_SRC					12
#define CAM_CC_CORE_AHB_CLK					13
#define CAM_CC_CPAS_AHB_CLK					14
#define CAM_CC_CPAS_BPS_CLK					15
#define CAM_CC_CPAS_FAST_AHB_CLK				16
#define CAM_CC_CPAS_IFE_0_CLK					17
#define CAM_CC_CPAS_IFE_1_CLK					18
#define CAM_CC_CPAS_IFE_LITE_CLK				19
#define CAM_CC_CPAS_IPE_NPS_CLK					20
#define CAM_CC_CPHY_RX_CLK_SRC					21
#define CAM_CC_CSI0PHYTIMER_CLK					22
#define CAM_CC_CSI0PHYTIMER_CLK_SRC				23
#define CAM_CC_CSI1PHYTIMER_CLK					24
#define CAM_CC_CSI1PHYTIMER_CLK_SRC				25
#define CAM_CC_CSI4PHYTIMER_CLK					26
#define CAM_CC_CSI4PHYTIMER_CLK_SRC				27
#define CAM_CC_CSID_CLK						28
#define CAM_CC_CSID_CLK_SRC					29
#define CAM_CC_CSID_CSIPHY_RX_CLK				30
#define CAM_CC_CSIPHY0_CLK					31
#define CAM_CC_CSIPHY1_CLK					32
#define CAM_CC_CSIPHY4_CLK					33
#define CAM_CC_FAST_AHB_CLK_SRC					34
#define CAM_CC_GDSC_CLK						35
#define CAM_CC_ICP_AHB_CLK					36
#define CAM_CC_ICP_CLK						37
#define CAM_CC_ICP_CLK_SRC					38
#define CAM_CC_IFE_0_CLK					39
#define CAM_CC_IFE_0_CLK_SRC					40
#define CAM_CC_IFE_0_DSP_CLK					41
#define CAM_CC_IFE_0_FAST_AHB_CLK				42
#define CAM_CC_IFE_1_CLK					43
#define CAM_CC_IFE_1_CLK_SRC					44
#define CAM_CC_IFE_1_DSP_CLK					45
#define CAM_CC_IFE_1_FAST_AHB_CLK				46
#define CAM_CC_IFE_LITE_AHB_CLK					47
#define CAM_CC_IFE_LITE_CLK					48
#define CAM_CC_IFE_LITE_CLK_SRC					49
#define CAM_CC_IFE_LITE_CPHY_RX_CLK				50
#define CAM_CC_IFE_LITE_CSID_CLK				51
#define CAM_CC_IFE_LITE_CSID_CLK_SRC				52
#define CAM_CC_IPE_NPS_AHB_CLK					53
#define CAM_CC_IPE_NPS_CLK					54
#define CAM_CC_IPE_NPS_CLK_SRC					55
#define CAM_CC_IPE_NPS_FAST_AHB_CLK				56
#define CAM_CC_IPE_PPS_CLK					57
#define CAM_CC_IPE_PPS_FAST_AHB_CLK				58
#define CAM_CC_JPEG_CLK						59
#define CAM_CC_JPEG_CLK_SRC					60
#define CAM_CC_MCLK0_CLK					61
#define CAM_CC_MCLK0_CLK_SRC					62
#define CAM_CC_MCLK1_CLK					63
#define CAM_CC_MCLK1_CLK_SRC					64
#define CAM_CC_MCLK2_CLK					65
#define CAM_CC_MCLK2_CLK_SRC					66
#define CAM_CC_MCLK3_CLK					67
#define CAM_CC_MCLK3_CLK_SRC					68
#define CAM_CC_MCLK4_CLK					69
#define CAM_CC_MCLK4_CLK_SRC					70
#define CAM_CC_MCLK5_CLK					71
#define CAM_CC_MCLK5_CLK_SRC					72
#define CAM_CC_MCLK6_CLK					73
#define CAM_CC_MCLK6_CLK_SRC					74
#define CAM_CC_MCLK7_CLK					75
#define CAM_CC_MCLK7_CLK_SRC					76
#define CAM_CC_PLL0						77
#define CAM_CC_PLL0_OUT_EVEN					78
#define CAM_CC_PLL0_OUT_ODD					79
#define CAM_CC_PLL1						80
#define CAM_CC_PLL1_OUT_EVEN					81
#define CAM_CC_PLL2						82
#define CAM_CC_PLL3						83
#define CAM_CC_PLL3_OUT_EVEN					84
#define CAM_CC_PLL4						85
#define CAM_CC_PLL4_OUT_EVEN					86
#define CAM_CC_PLL5						87
#define CAM_CC_PLL5_OUT_EVEN					88
#define CAM_CC_QDSS_DEBUG_CLK					89
#define CAM_CC_QDSS_DEBUG_CLK_SRC				90
#define CAM_CC_QDSS_DEBUG_XO_CLK				91
#define CAM_CC_SLEEP_CLK					92
#define CAM_CC_SLEEP_CLK_SRC					93
#define CAM_CC_SLOW_AHB_CLK_SRC					94
#define CAM_CC_XO_CLK_SRC					95

/* CAM_CC power domains */
#define CAM_CC_BPS_GDSC						0
#define CAM_CC_IFE_0_GDSC					1
#define CAM_CC_IFE_1_GDSC					2
#define CAM_CC_IPE_0_GDSC					3
#define CAM_CC_TITAN_TOP_GDSC					4

/* CAM_CC resets */
#define CAM_CC_BPS_BCR						0
#define CAM_CC_ICP_BCR						1
#define CAM_CC_IFE_0_BCR					2
#define CAM_CC_IFE_1_BCR					3
#define CAM_CC_IPE_0_BCR					4
#define CAM_CC_QDSS_DEBUG_BCR					5

#endif
